1. Field of the Invention
The present invention relates to semiconductor memory devices, and more particularly, to a structure of a static random access memory (referred to as SRAM hereinafter).
2. Description of the Background Art
As shown in FIG. 19, a memory cell of a conventional SRAM includes, a total of six elements i.e. four N type transistors (two access transistors Q1 and Q2, and two driver transistors Q3 and Q4), and two P type transistors (load transistors Q5 and Q6) a total of six elements. Since the six transistors are formed on the surface of a semiconductor substrate, there was a disadvantage that the cell size is increased.
Conventionally, a TFT (Thin Film Transistor) is used as a P type transistor to form four elements on the surface of the semiconductor substrate and two elements of the TFT above the semiconductor substrate to reduce the cell size.
It has become difficult to obtain a stable operation at a low voltage of not more than 3 V using a TFT load. This is because favorable current performance of a TFT cannot be obtained at a low voltage. The usage of a P type transistor formed on the surface of a semiconductor substrate of favorable current performance as a P type transistor is proposed for the purpose of achieving a stable operation at a low voltage. This is disclosed in, for example, IEICE TRANS. ELECTRON., VOL. E77-C, NO. 8 August 1994, pp. 1385-1394.
A layout of a memory cell of a SRAM disclosed in this document is shown in FIGS. 20 and 21. Referring to FIG. 20, a conventional memory cell disclosed in this document includes two access transistors Q1 and Q2 of N type MOS transistors at a main surface of a semiconductor substrate (not shown), two driver transistors Q3 and Q4 of N type MOS transistors, and two load transistors Q5 and Q6 of P type MOS transistors. An N type MOS active region 1 is provided so as to form the source/drain region of an N type MOS transistor. A P type MOS active region 6 is provided so as to form the source/drain region of a P type MOS transistor.
A trench isolation region 203 is formed in a region other than where N type MOS active region 1 and P type MOS active region 6 are formed on the surface of the semiconductor substrate. A word line 3 is formed of a first polycide layer also forming the gate electrodes of access transistors Q1 and Q2 is formed. Also, a gate electrode 3b of driver transistor Q3 and load transistor Q5, and a gate electrode 3c of driver transistor Q4 and load transistor Q6 are both formed of the first polycide layer. First polycide layers 3b and 3c are connected to active regions 1 and 6 by a first polycontact 7. Furthermore, a second polycide layer that will be described afterwards is connected to active regions 1 and 6 by a second polycontact 8.
FIG. 21 is a conceivable diagram not actually disclosed, but that can be derived from the aforementioned document. A GND wiring 9b formed of a second polycide layer is connected to active region 1 (refer to FIG. 20) via a second polycontact 8. A Vcc wiring 9c formed of a second polycide layer is connected to PMOS active region 6 via second polycontact 8. In NMOS active region 1 of access transistors Q1 and Q2, a pad layer 9a of the second polycide layer is formed via second polycontact 8. Pad layer 9a and a pair of bit lines 10 formed of a metal wiring are connected via contact 11.
FIG. 22 is an equivalent circuit diagram corresponding to the layout of FIGS. 20 and 21, and FIG. 23 is a general rewritten equivalent circuit virsion of the equivalent circuit of FIG. 22. Referring to FIGS. 22 and 23, the node of access transistor Q1 and driver transistor Q3 is a storage node 12. The node between access transistor Q2 and driver transistor Q4 is a storage node 13. There is no first polycontact 7 in a current path I1. In contrast, two first polycontacts 7 are present in a current path I2.
FIG. 24 is a sectional view of the memory cell of FIG. 20 taken along line 200--200. Referring to FIG. 24, an N well 202 and a P.sup.- well 201 are formed adjacent to each other on the surface of a semiconductor substrate 201 corresponding to a PMOS region and an NMOS region, respectively. A trench isolation 203 is formed at the main surface of semiconductor substrate 201 except where active regions 1 and 6 are formed. Furthermore, a p.sup.+ impurity region 205 forming the source/drain region of load transistor Q6 is provided at a predetermined region of the main surface of N.sup.- well 202. An n.sup.+ impurity region 204 forming the source/drain region of driver transistor Q4 is provided at a predetermined region of the main surface of P.sup.- well 201. An oxide film 206 is formed on the main surface of semiconductor substrate 201. First polycontact 7 is formed in a region of oxide film 206 located above p.sup.+ and n.sup.+ impurity regions 205 and 204.
A third gate electrode 3b of the first polycide layer is formed in first polycontact 7 so as to electrically connect p.sup.+ impurity region 205 and n.sup.+ impurity region 204, and so as to extend along the main surface of oxide film 206. Gate electrode 3b includes an n type polysilicon layer 30, a p type polysilicon layer 31 formed integral with n type polysilicon layer 30, and a WSi layer 32 formed on the surface of n type polysilicon layer 30 and p type polysilicon layer 31. Such a structure of having a gate electrode of a PMOS transistor formed of a P type polysilicon layer 31 and a gate electrode of an NMOS transistor formed of an N type polysilicon layer 30 is called a dual gate transistor. When this dual gate transistor employs an N type polysilicon layer as the gate electrode of a conventional PMOS transistor, the formation of a PN junction at the connection of the N type polysilicon layer and p.sup.+ impurity region 205 of the P type transistor is prevented.
As shown in FIG. 23, the above-described conventional SRAM includes no first polycontact 7 in current path I1 and two first polycontacts 7 in current path I2. This means that current path I2 has a contact resistance greater than that of current path I1 by the two first polycontacts 7. Therefore, the current flowing across current path I2 is smaller than that flowing across current path I1. As a result, a readout is delayed when current flows at the current path I2 side (when storage node 13 has a L data). There was a disadvantage of imbalance in the electric characteristics due to different resistances between current path I1 and current path I2 in a conventional memory cell.
Since gate electrode 3a of access transistors Q1 and Q2, gate electrode 3b of driver transistor Q3 and load transistor Q5, and gate electrode 3b of driver transistor Q4 and load transistor Q6 are formed of a first polycide layer in the memory cell of the conventional SRAM shown in FIGS. 21 and 22, it is not possible to overlap gate electrodes 3a, 3b and 3c. Therefore, it was difficult to reduce the memory size.
Furthermore, since the memory cell of a conventional SRAM has a dual gate transistor structure of a P type polysilicon layer 31 and an N type polysilicon layer 30 as shown in FIG. 24, there was a disadvantage that the boron means P type polysilicon layer 31 is penetrated through gate oxide film 206. In this case, there was a problem that the threshold voltage of the P type transistor is altered.
In the dual gate transistor shown in FIG. 24, the P type impurities of boron in P type polysilicon layer 31 are easily diffused to the upper WSi layer 32. There was a disadvantage that boron is introduced into the N type polysilicon layer to vary the threshold voltage V.sub.TH. There was a problem that the resistance value of the gate electrode is altered. For the purpose of solving this problem, an approach is proposed of suppressing boron diffusion by providing an amorphous silicon layer (not shown) between the lower polysilicon layer 31 and the upper WSi layer 32. However, this approach induces another problem that an extra process of forming an amorphous silicon layer is required. The formation of an amorphous silicon layer results in increase in the height of gate electrode 3b to become a bottleneck in reducing the step portion for a thinner gate electrode. Therefore, offset in focus in forming a fine pattern by photolithography becomes greater to reduce the focus margin.